1. Field of the Invention
The present invention relates to semiconductor packaging and methods for packaging semiconductor devices. More particularly, the invention relates to a PoP (package-on-package) using thin or coreless substrates.
2. Description of Related Art
Package-on-package (“PoP”) technology has become increasingly popular as the demand for lower cost, higher performance, increased integrated circuit density, and increased package density continues in the semiconductor industry. As the push for smaller and smaller packages increases, the integration of die and package (e.g., “pre-stacking” or the integration of system on a chip (“SoC”) technology with memory technology) allows for thinner packages. Such pre-stacking has become a critical component for thin and fine pitch PoP packages.
A problem that arises with thin and fine pitch PoP packages is the potential for warping as the pitch is reduced between terminals (e.g., balls such as solder balls) on either the top package or the bottom package in the PoP package. Warping may be caused by the difference in thermal characteristics of materials used in the package (e.g., the substrate and an encapsulant applied to the substrate). The top package may especially have warping problems due to the top package not being attached to any external component that inhibits warping. For example, the bottom package may be attached to a printed circuit board that helps to inhibit warping in the bottom package.
The warping problem in the top package may be further increased with the use of a thin or coreless substrate in the top package. The thin or coreless substrate may have less mechanical strength to resist the effects caused by differences in thermal characteristics between the substrate and the applied encapsulant. The warping problem may lead to failure or reduced performance of the PoP package and/or problems in reliability of devices utilizing the PoP package.